diff --git a/.vale.ini b/.vale.ini
index cb4fc67..2ef6216 100644
--- a/.vale.ini
+++ b/.vale.ini
@@ -2,7 +2,7 @@ StylesPath = styles
 
 MinAlertLevel = suggestion
 
-Packages = write-good
+Packages = write-good, proselint
 
 [*.{md}]
 # ^ This section applies to only Markdown files.
@@ -14,5 +14,6 @@ Packages = write-good
 # Markdown and reStructuredText:
 #
 # [*.{md,rst}]
-BasedOnStyles = Vale, write-good
+BasedOnStyles = Vale, write-good, proselint
 
+write-good.E-Prime = NO
diff --git a/content/blog/yosys4gal/yosys4gal.md b/content/blog/yosys4gal/yosys4gal.md
index 9c76c70..193ede0 100644
--- a/content/blog/yosys4gal/yosys4gal.md
+++ b/content/blog/yosys4gal/yosys4gal.md
@@ -7,15 +7,15 @@ date: 2024-06-14
 ## A history lesson
 
 During the semiconductor revolution, a dilemma appeared: Designing new ICs
-required a lot of time and effort to create the mask, and iteration was
-expensive. At the time, IC designs were very simple, since the available
+required a lot of time and effort to create the mask, and iteration
+expensive. Due to limited compute capability, ICs could not be complex designs.
 tools/compute to do tasks like optimization or place-and-route were limited.
 And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs)
 were an early approach to these problems. The idea was simple: create a
 flexible logic architecture that could be modified later in the process to
-implement various digital designs. These worked by using matrices of wires in a
+implement digital designs. These worked by using matrices of wires in a
 Sum-of-Products architecture. Inputs would be fed with their normal and
-inverted forms to a bank of AND gates, which would select various inputs using
+inverted forms to a bank of AND gates, which would select inputs using
 a fuse tie on the die and create product terms. The outputs of the AND gates
 would then be fed into OR gates, which would create the sum term for the whole
 output.
@@ -30,14 +30,15 @@ it, make some adjustments, and then program the next. Later versions would
 solve the whole one-time-programmable aspect using UV-erasable EEPROM.
 
 
-![A figure shows the structure of a PLA. There is a grid of wires that is fed into the inputs of AND gates. The AND gates are then selected by a set of OR gates.](pla_logic2.svg "Old School PLA.")
+![A figure shows the structure of a PLA. A grid of perpendicular wires connects the inputs of AND gates. The AND gates feed in to a set of OR gates.](pla_logic2.svg "Old School PLA."
 
 Demands would increase further and flip-flops would be added, as well as
-feedback capability. This allows for very complex functions to be implemented,
-since you can chain "rows" of the output blocks. This culminated in the
-GAL22V10, which was an electronically-erasable, 22-pin programmable logic
-block, which had up to 10 outputs that could be registered and used for
-feedback.
+feedback capability. This allows for implementation of functions that would
+otherwise be too large to fit in a single logic term, since you can chain
+"rows" of the output blocks. This culminated in the GAL22V10, which is an
+electronically-erasable, 22-pin programmable logic block, which had up to 10
+outputs that are registered and used for feedback. These outputs can be tri-stated
+to give greater flexibility.
 
 ![A figure shows the Output Logic Macrocell, or OLMC. The OLMC consists of a D Flip-Flop, feedback routing, and 4-to-1 mux to select behavior](gal_olmc.png)
 
@@ -47,9 +48,9 @@ These days, modern FPGA technology can be yours for a couple of bucks.
 Open-source toolchains allow fast, easy development, and the glut of Verilog
 resources online makes it easier than ever to enter the world of hardware
 design. But there are times when GALs might still be useful. For one, they
-start up instantly. Some FPGAs have a very fast one-time- programmable internal
+start up instantly. Some FPGAs have a fast one-time-programmable internal
 ROM, but this loses the "field-programmable" aspect which makes FPGAs
-desirable. In most cases the bitstream must be loaded from an external SPI
+desirable. In most cases the bitstream loads from an external SPI
 flash. This can take up to a few seconds, which may not be acceptable if the
 logic is critical. Another important factor is the chip packaging. Most FPGAs
 are BGA packages, with some offering QFN or even a few QFP variants, but none
@@ -102,13 +103,14 @@ the chip, and even integrate our designs with FPGAs later down the line.
 
 # The idea
 
-GAL assembly is still common
+GAL assembly appears occasionally when working with older systems, especially in a retro emulation context.
+
 
 # Is this useful?
 
 Not particularly.
 
-Well, there's an extremely niche use case. These parts are 5-volt tolerant, and
+Well, there is a niche use case. These parts are 5-volt tolerant, and
 come in DIP packages. If you needed some basic glue logic when working on an
 older 5 volt system, you might want to have a few of these and a programmer
 instead of a collection of 74-series logic. At the very least, these chips can