more content

content/blog/yosys4gal/yosys4gal.md

@@ -4,6 +4,71 @@ description: Bringing modern synthesis to 30-year old technology with Yosys and
 date: 2024-06-14
 ---
 
+
+
+GAL/PALs are ancient chips designed to implement custom logic as a precursor to CPLDs and FPGAs.
+They can implement any combinational logic using a Sum-of-Products architecture and a grid of wires
+with certain wires being connected at different coordinates:
+
+![A figure shows the structure of a PLA. A grid of perpendicular wires connects the inputs of AND gates. The AND gates feed in to a set of OR gates.](pla_logic2.svg "Old School PLA.")
+
+Later GALs added more features like feedback, tri-state pins, and D Flip-Flops for sequential logic.
+
+![A figure shows the Output Logic Macro-cell, or OLMC. The OLMC consists of a D Flip-Flop, feedback routing, and 4-to-1 mux to select behavior](gal_olmc.png)
+
+They're pretty neat, except for the part where they're a nightmare to program. Instead of using Verilog or other HDLs,
+which didn't exist at the time, designers would manually specify the terms of each output:
+
+```palasm
+gal16v8
+CombTest
+
+Clock I0    I1    I2    I3    I4    I5    NC    NC   GND
+/OE   O0    O1    O2    O3    O4    I6    NC    NC   VCC
+
+O0 = I0 * I1
+
+O1 = I2 + I3 + I6
+
+O2 = I4 * /I5 + /I4 * I5
+
+O3 = I0 * I1 * I2 * I3 * I4 * I5
+
+/O4 = I0 + I1 + I2 + I3 + I4 + I5
+
+DESCRIPTION
+
+Simple test of combinatorial logic.
+```
+
+
+I don't want to deal with this. It's annoying to think about. What if we could create our own Verilog flow for GAL chips?
+Then we could take advantage of the simulation and synthesis capabilities, which would make these chips a bit more useful.
+
+
+# The idea
+
+We use Yosys to synthesize Verilog, and do technology-mapping onto a set of primitive blocks that are then mapped by a custom tool.
+Our custom tool takes the place of `nextpnr` in the standard open-source gateware flow. It will be responsible for mapping the techmap
+onto actual positions based on a pin constraints file.
+
+There's two components - Yosys technology mapping, and writing a "place-and-route" tool. We'll start with Yosys.
+
+
+
+## Yosys Technology Mapping
+
+This process is cursed and low level, but it works a little like this:
+
+- Yosys takes a generic synthesis pass at a netlist, which simplifies the design without looking at any physical implementation
+- The simplified design is then mapped into Verilog-based "blocks", which could be things like AND gates, or complex blocks like a LUT.
+This process turns generic blocks like an adder into a set of gates.
+- certain sequences of gates are then grouped and unified in the "extract" pass. Extraction would convert an operation like `mul -> add`
+into a single `mul_add` block.
+
+
+
+
 ## A history lesson
 
 During the semiconductor revolution, a dilemma appeared: Designing new integrated circuits
@@ -12,8 +77,8 @@ expensive. Due to limited tooling, ICs could not be complex designs.
 Techniques and tools to do tasks like optimization or place-and-route did not exist or were primitive.
 And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs)
 were an early approach to these problems. The idea was simple: create a
-flexible logic architecture that could be modified later in the process to
+flexible logic architecture to allow for engineers to prototype new
-implement digital designs. These worked by using matrices of wires in a
+digital designs. These worked by using matrices of wires in a
 Sum-of-Products architecture. Inputs would be fed with their normal and
 inverted forms to a bank of AND gates, which would select inputs using
 a fuse tie on the die and create product terms. The outputs of the AND gates
@@ -22,23 +87,23 @@ output.
 
 This design was popular, since it allowed for less-certain aspects of the chip
 to be moved to a later design process. Eventually, hardware people got jealous
-of the fast (for the time) compile-evaluate loops in software, and so PAL
+of the fast (for the time) compile-eval loops in software, and so some smart engineers created PAL
-(Programmable Array Logic) was invented. These are similar to PLA logic, but
+(Programmable Array Logic).PAL is similar to PLA logic, but
 the fuses are programmed using a simple programmer rather than a complex die
 process. This means that a developer with a pile of chips can program one, test
 it, make some adjustments, and then program the next. Later versions would
 solve the whole one-time-programmable aspect using UV-erasable EEPROM.
 
-
+![A figure shows the structure of a PLA. A grid of perpendicular wires connects the inputs of AND gates. The AND gates feed in to a set of OR gates.](pla_logic2.svg "Old School PLA.")
-![A figure shows the structure of a PLA. A grid of perpendicular wires connects the inputs of AND gates. The AND gates feed in to a set of OR gates.](pla_logic2.svg "Old School PLA."
 
 Demands would increase further and flip-flops would be added, as well as
 feedback capability. This allows for implementation of functions that would
 otherwise be too large to fit in a single logic term, since you can chain
 "rows" of the output blocks. This culminated in the GAL22V10, which is an
 electronically-erasable, 22-pin programmable logic block, which had up to 10
-outputs that are registered and used for feedback. These outputs can be tri-stated
+outputs that are registered and used for feedback. These outputs are also
-to give greater flexibility.
+capable of tri-state (input or output switchable during operation) to give
+greater flexibility.
 
 ![A figure shows the Output Logic Macro-cell, or OLMC. The OLMC consists of a D Flip-Flop, feedback routing, and 4-to-1 mux to select behavior](gal_olmc.png)
 
@@ -66,8 +131,8 @@ removes the need for a level shifter.
 In practice, this isn't all great. Programming GALs is an exercise in frustration.
 Take a look at a basic combinatorial assembly file:
 
-```PALASM
+```palasm
-GAL16V8
+gal16v8
 CombTest
 
 Clock I0    I1    I2    I3    I4    I5    NC    NC   GND