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92bcb1e4b9
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f89bb2c6da
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.gitignore
vendored
12
.gitignore
vendored
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@ -5,11 +5,11 @@ result
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# Vale
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# Vale
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/styles/*
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./styles/*
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!/styles/config/
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!./styles/config/
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/styles/config/*
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./styles/config/*
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!/styles/config/vocabularies/
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!./styles/config/vocabularies/
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/styles/config/vocabularies/*
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./styles/config/vocabularies/*
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!/styles/config/vocabularies/Base
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!./styles/config/vocabularies/Base
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@ -4,8 +4,6 @@ MinAlertLevel = suggestion
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Packages = write-good, proselint
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Packages = write-good, proselint
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Vocab = Base
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[*.{md}]
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[*.{md}]
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# ^ This section applies to only Markdown files.
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# ^ This section applies to only Markdown files.
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#
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#
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@ -1,9 +0,0 @@
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---
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title: Hacking Hikmicro part 1
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description: Reverse engineering the Hikmicro Pocket C to understand the image format
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---
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I recently picked up a Hikmicro Pocket C thermal imager, since
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my old Seek Thermal was becoming too annoying to use. The Pocket
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C is a standalone device with a much better sensor. It supports
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radiometric images as well as radiometric video and USB radio.
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@ -6,10 +6,10 @@ date: 2024-06-14
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## A history lesson
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## A history lesson
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During the semiconductor revolution, a dilemma appeared: Designing new integrated circuits
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During the semiconductor revolution, a dilemma appeared: Designing new ICs
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required a lot of time and effort to create the mask, and iteration
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required a lot of time and effort to create the mask, and iteration
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expensive. Due to limited tooling, ICs could not be complex designs.
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expensive. Due to limited compute capability, ICs could not be complex designs.
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Techniques and tools to do tasks like optimization or place-and-route did not exist or were primitive.
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tools/compute to do tasks like optimization or place-and-route were limited.
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And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs)
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And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs)
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were an early approach to these problems. The idea was simple: create a
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were an early approach to these problems. The idea was simple: create a
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flexible logic architecture that could be modified later in the process to
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flexible logic architecture that could be modified later in the process to
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@ -40,7 +40,7 @@ electronically-erasable, 22-pin programmable logic block, which had up to 10
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outputs that are registered and used for feedback. These outputs can be tri-stated
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outputs that are registered and used for feedback. These outputs can be tri-stated
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to give greater flexibility.
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to give greater flexibility.
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## Back To Today: GALs in the 21st Century
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## Back To Today: GALs in the 21st Century
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@ -63,7 +63,7 @@ GALs operate at 5 volts is useful when interfacing with older systems and
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removes the need for a level shifter.
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removes the need for a level shifter.
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In practice, this isn't all great. Programming GALs is an exercise in frustration.
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However, this isn't all great. Programming GALs is an exercise in frustration.
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Take a look at a basic combinatorial assembly file:
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Take a look at a basic combinatorial assembly file:
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```PALASM
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```PALASM
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@ -113,7 +113,7 @@ Not particularly.
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Well, there is a niche use case. These parts are 5-volt tolerant, and
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Well, there is a niche use case. These parts are 5-volt tolerant, and
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come in DIP packages. If you needed some basic glue logic when working on an
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come in DIP packages. If you needed some basic glue logic when working on an
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older 5 volt system, you might want to have a few of these and a programmer
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older 5 volt system, you might want to have a few of these and a programmer
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instead of a collection of 74-series logic. These chips can
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instead of a collection of 74-series logic. At the very least, these chips can
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emulate any 74-series chip, and can reduce a multi-chip design to a single
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emulate any 74-series chip, and can reduce a multi-chip design to a single
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chip. The DIP form factor makes it much easier to breadboard, and the chips
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chip. The DIP form factor makes it much easier to breadboard, and the chips
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have zero start up delay.
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have zero start up delay.
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@ -1,5 +1,6 @@
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export default {
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export default {
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tags: [
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tags: [
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"posts"
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],
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],
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"layout": "layouts/deck.njk",
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"layout": "layouts/deck.njk",
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};
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};
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@ -1,18 +0,0 @@
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Verilog
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FPGAs?
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Yosys
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ICs?
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PLAs?
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toolchains?
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testbench(es)?
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bitstream
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gateware
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mux
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# Terms for electronics
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GALs?
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BGA
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DIP
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SSOP
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QF[PN]
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