coordinator works now

fixed some off by one errors to make the screen work good

verilog/tb/coordinator_tb.sv

@@ -7,7 +7,7 @@ coordinator dut(.clk(clk));
   initial begin
     $dumpfile("coordinator.vcd");
     $dumpvars(0, coordinator_tb);
-    repeat (10000) @(posedge clk);
+    repeat (100000) @(posedge clk);
     $finish;
   end
 endmodule