generated from saji/litex-overlay
115 lines
3.9 KiB
Python
115 lines
3.9 KiB
Python
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# r0 g0 b0 gnd r1 g1 b1 e a b c d clk stb oe gnd
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from litex.build.generic_platform import Signal, Subsignal, Pins
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from litex.build.io import FSM, Module, Cat, Replicate
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from litex.gen import ClockSignal, If, Instance, NextState, NextValue
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def make_hub75_iodevice(index, basename):
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b = basename
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signals = ("hub75_iodev", index,
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Subsignal("r0", Pins(f"{b}:0")),
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Subsignal("g0", Pins(f"{b}:1")),
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Subsignal("b0", Pins(f"{b}:2")),
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Subsignal("r1", Pins(f"{b}:4")),
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Subsignal("g1", Pins(f"{b}:5")),
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Subsignal("b1", Pins(f"{b}:6")),
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Subsignal("addr", Pins(f"{b}:8 {b}:9 {b}:10 {b}:11 {b}:7")),
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Subsignal("clk", Pins(f"{b}:12")),
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Subsignal("stb", Pins(f"{b}:13")),
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Subsignal("oe", Pins(f"{b}:14")),
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)
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return [signals]
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class Hub75Driver(Module):
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def __init__(self, base_freq=60e6, linedepth=128):
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if base_freq // 2 > 30e6:
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raise RuntimeError("hi")
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self.addr = Signal(5)
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self.latch = Signal()
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self.output_en = Signal()
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color = Signal(24, reset=0xA0FF00)
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self.rgb = Signal(6)
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self.clock_out = Signal()
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self.fsm = fsm = FSM()
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self.submodules += self.fsm
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bcm_value = Signal(3)
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counter = Signal(32)
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should_expose = (counter < (16 << bcm_value)) & (bcm_value != 0)
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# this state both sets the OE low to drive the display with the previous frame
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# while also loading the next row
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# FIXME: there's a bug on the starting conditions right now, we are losing the lowest bit.
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fsm.act("WRITEROW",
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self.output_en.eq(~should_expose),
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self.rgb[0].eq((color >> bcm_value) & 1),
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self.rgb[3].eq((color >> bcm_value) & 1),
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self.rgb[1].eq((color >> (bcm_value + 8)) & 1),
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self.rgb[4].eq((color >> (bcm_value + 8)) & 1),
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self.rgb[2].eq((color >> (bcm_value + 16)) & 1),
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self.rgb[5].eq((color >> (bcm_value + 16)) & 1),
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NextValue(counter, counter + 1),
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If(counter < linedepth * 2,
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self.clock_out.eq(counter[0]),
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),
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If(~(counter < linedepth * 2) & ~should_expose,
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NextValue(counter, 0),
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NextState("LATCH"),
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),
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)
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fsm.act("EXPOSE",
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self.output_en.eq(0),
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If(counter < (16 << bcm_value),
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NextValue(counter, counter + 1),
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).Else(
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NextValue(counter, 0),
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NextState("LATCH"),
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),
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)
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fsm.act("LATCH",
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self.latch.eq(1),
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self.output_en.eq(1),
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NextValue(counter, 0),
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If(bcm_value == 7,
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NextValue(bcm_value, 0),
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NextValue(self.addr, self.addr + 1),
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).Else(
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NextValue(bcm_value, bcm_value + 1),
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),
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NextState("WRITEROW"),
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)
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class Hub75VerilogDriver(Module):
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def __init__(self):
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self.o_addr = Signal(5)
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self.o_display_clk = Signal()
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self.o_latch = Signal()
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self.o_out_enable = Signal()
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self.o_panel_rgb0 = Signal(3)
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self.o_panel_rgb1 = Signal(3)
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inst = Instance("coordinator",
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i_clk = ClockSignal(),
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o_panel_rgb0 = self.o_panel_rgb0,
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o_panel_rgb1 = self.o_panel_rgb1,
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o_latch = self.o_latch,
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o_display_clk = self.o_display_clk,
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o_out_enable = self.o_out_enable,
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o_display_addr = self.o_addr,
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)
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self.specials += inst
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