generated from saji/litex-overlay
122 lines
3.8 KiB
Python
122 lines
3.8 KiB
Python
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# r0 g0 b0 gnd r1 g1 b1 e a b c d clk stb oe gnd
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from litex.build.generic_platform import Signal, Subsignal, Pins
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from litex.build.io import FSM, Module
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from litex.gen import If, NextState, NextValue
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from migen import Cat
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def make_hub75_iodevice(index, basename):
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b = basename
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signals = ("hub75_iodev", index,
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Subsignal("r0", Pins(f"{b}:0")),
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Subsignal("g0", Pins(f"{b}:1")),
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Subsignal("b0", Pins(f"{b}:2")),
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Subsignal("r1", Pins(f"{b}:4")),
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Subsignal("g1", Pins(f"{b}:5")),
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Subsignal("b1", Pins(f"{b}:6")),
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Subsignal("addr", Pins(f"{b}:8 {b}:9 {b}:10 {b}:11 {b}:7")),
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Subsignal("clk", Pins(f"{b}:12")),
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Subsignal("stb", Pins(f"{b}:13")),
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Subsignal("oe", Pins(f"{b}:14")),
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)
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return [signals]
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class Hub75Driver(Module):
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def __init__(self, base_freq=60e6, linedepth=128):
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if base_freq // 2 > 30e6:
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raise RuntimeError("hi")
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self.phase = Signal() # divider/counter
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self.addr = Signal(5)
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self.latch = Signal()
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self.output_en = Signal()
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self.rgb = Signal(6, reset=0b111010)
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# clk-en acts as a gate.
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clock_en = Signal()
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self.clock_out = Signal()
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self.fsm = fsm = FSM()
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self.submodules += self.fsm
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bcm_value = Signal(3)
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counter = Signal(32)
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fsm.act("WRITEROW",
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self.output_en.eq(1),
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If(counter < 256,
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self.clock_out.eq(counter[0]),
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NextValue(counter, counter + 1),
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If(counter[0], NextValue(self.rgb, self.rgb + 3)),
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).Else(
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NextValue(counter, 0),
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NextState("EXPOSE"),
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),
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)
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fsm.act("EXPOSE",
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self.output_en.eq(0),
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If(counter < (1000 << bcm_value),
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NextValue(counter, counter + 1),
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).Else(
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NextValue(counter, 0),
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NextState("LATCH"),
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),
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)
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fsm.act("LATCH",
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self.latch.eq(1),
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NextValue(counter, 0),
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If(bcm_value == 7,
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NextValue(bcm_value, 0),
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NextValue(self.addr, self.addr + 1),
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).Else(NextValue(bcm_value, 1)),
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NextState("WRITEROW"),
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)
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# fsm.act("ready",
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# NextValue(self.output_en, 1),
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# NextValue(self.pixnum, linedepth - 1),
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# NextValue(self.latch, 0),
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# If(self.phase == 1,
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# NextValue(self.addr, self.addr + 1),
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# NextValue(clock_en, 1),
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# NextState("transmit"),
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# ),
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# # If((self.state_count == 7), NextValue(clock_en, ~clock_en)),
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# )
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# fsm.act("transmit",
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# If(self.phase == 1,
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# NextValue(self.pixnum, self.pixnum - 1),
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# If(self.pixnum == 0,
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# NextState("latch_delay"),
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# )
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# )
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# )
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# fsm.act("latch_delay",
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# NextValue(clock_en, 0),
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# If(self.phase == 1,
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# NextState("latchout")
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# )
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# )
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# fsm.act("latchout",
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# If(self.phase == 1,
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# NextValue(self.latch, 1),
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# NextValue(counter, 0),
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# NextState("done")
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# )
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# )
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# fsm.act("done",
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# NextValue(self.output_en, 0),
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# NextValue(self.latch, 0),
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# NextValue(counter, counter + 1),
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# If(counter == 255, NextState("ready"))
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# )
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#
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