From fb7a8c2975ad964327b6611e16062e9f66bb6fa1 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Sat, 24 Aug 2024 18:19:19 +0300
Subject: [PATCH] cxxrtl: add externals.

Just assuming all (plain) Verilog for now.
---
 niar/cxxrtl.py | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/niar/cxxrtl.py b/niar/cxxrtl.py
index 9e94698..ca8fdf6 100644
--- a/niar/cxxrtl.py
+++ b/niar/cxxrtl.py
@@ -136,6 +136,11 @@ def main(np: Project, args):
         with open(yosys_script_path, "w") as f:
             for box_source in black_boxes.values():
                 f.write(f"read_rtlil <<rtlil\n{box_source}\nrtlil\n")
+            for p in np.externals:
+                f.write(f"read_verilog <<niar_read_verilog\n")
+                with open(np.path(p), 'r') as r:
+                    f.write(r.read())
+                f.write(f"\nniar_read_verilog\n")
             f.write(f"read_rtlil {_make_absolute(il_path)}\n")
             if args.optimize.opt_rtl:
                 f.write("opt\n")