yosys4gal/testcases/test.v

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module test (
	input clk,

	output reg [0:7] counter
);

always @ (posedge clk) begin
	counter <= counter + 1;
end

endmodule

/*module test (
	input [1:0] a, b,
	output [2:0] y
);

assign y = a + b;

endmodule*/
initial commit 2024-03-18 05:06:49 +00:00			`module test (`
			`input clk,`

			`output reg [0:7] counter`
			`);`

			`always @ (posedge clk) begin`
make TCL 2024-03-18 07:12:59 +00:00			`counter <= counter + 1;`
initial commit 2024-03-18 05:06:49 +00:00			`end`

			`endmodule`

			`/*module test (`
			`input [1:0] a, b,`
			`output [2:0] y`
			`);`

			`assign y = a + b;`

			`endmodule*/`