mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2025-05-06 14:43:11 +00:00
9 lines
81 B
Verilog
9 lines
81 B
Verilog
module and_gate (A, B, Y);
|
|
|
|
input A, B;
|
|
output Y;
|
|
|
|
assign Y = A && B;
|
|
|
|
endmodule
|