mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2025-05-06 14:43:11 +00:00
9 lines
76 B
Verilog
9 lines
76 B
Verilog
module big_xor (A, Y);
|
|
|
|
input [7:0] A;
|
|
output Y;
|
|
|
|
assign Y = ^A;
|
|
|
|
endmodule
|