saji/yosys4gal
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mirror of https://github.com/annoyatron255/yosys4gal.git synced 2025-05-06 14:43:11 +00:00
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Verilog Flow for the GAL16V8 and GAL22V10
45 commits 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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saji fb4ae03c91 fix 16v8 regression with tristate/registered 
Tristate can't be set on registered logic in 16V8. We add a check
to skip those.
2024-05-05 17:30:11 -05:00
compiler fix 16v8 regression with tristate/registered 2024-05-05 17:30:11 -05:00
extractions Add tristates 2024-04-04 20:39:30 -05:00
models Add tristate to equiv script 2024-05-04 21:23:50 -05:00
techmaps Ensure OLMC/SOP invariant with tristate 2024-05-05 00:20:18 -05:00
testcases Add tiny_xor testcase and convince ABC to work right 2024-05-05 03:20:30 -05:00
.gitignore Add gitignore and remove extra files 2024-05-04 20:59:57 -05:00
abc.script Add OLMCs 2024-04-04 01:33:47 -05:00
cells_sim.v Add tristates 2024-04-04 20:39:30 -05:00
flash_minipro.sh Complete prove_equiv script and add flashing script 2024-05-04 20:55:57 -05:00
shrink_sop.tcl Add shrink SOP and PCF files 2024-05-05 02:29:15 -05:00
synth_gal.tcl Add tiny_xor testcase and convince ABC to work right 2024-05-05 03:20:30 -05:00