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cxxrtl: add externals.

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Just assuming all (plain) Verilog for now.
This commit is contained in:
Asherah Connor 2024-08-24 18:19:19 +03:00
parent 594d92f3fd
commit fb7a8c2975
1 changed files with 5 additions and 0 deletions
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5
niar/cxxrtl.py
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@ -136,6 +136,11 @@ def main(np: Project, args):
with open(yosys_script_path, "w") as f: with open(yosys_script_path, "w") as f:
for box_source in black_boxes.values(): for box_source in black_boxes.values():
f.write(f"read_rtlil <<rtlil\n{box_source}\nrtlil\n") f.write(f"read_rtlil <<rtlil\n{box_source}\nrtlil\n")
for p in np.externals:
f.write(f"read_verilog <<niar_read_verilog\n")
with open(np.path(p), 'r') as r:
f.write(r.read())
f.write(f"\nniar_read_verilog\n")
f.write(f"read_rtlil {_make_absolute(il_path)}\n") f.write(f"read_rtlil {_make_absolute(il_path)}\n")
if args.optimize.opt_rtl: if args.optimize.opt_rtl:
f.write("opt\n") f.write("opt\n")