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Code Activity
82 commits 2 branches 3 tags 129 KiB
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Author SHA1 Message Date
Asherah Connor 944321f5d9 cmdrunner: report exit statuses. 2024-09-27 17:44:19 +10:00
Asherah Connor 6a0c97d1f5 cxxrtl: less traceback. 2024-09-27 17:32:55 +10:00
Asherah Connor 56234604d0 command: add. 2024-09-06 19:14:26 +03:00
Asherah Connor 2cbed9def8 cxxrtl: don't drop backtrace on ^C. 2024-09-05 18:34:16 +03:00
Asherah Connor 282e4447a3 flake.nix: use our amaranth fork again for now. 
packageOverrides doesn't compose, ugggggggh.
 2024-08-29 16:54:45 +03:00
Asherah Connor 4cb42dfedf pyproject.toml: allow amaranth >= 0.5. 2024-08-29 15:01:44 +03:00
Asherah Connor df82cbb17d cxxrtl: put externals separate to yosys script. 2024-08-24 22:24:28 +03:00
Asherah Connor fb7a8c2975 cxxrtl: add externals. 
Just assuming all (plain) Verilog for now.
 2024-08-24 18:19:19 +03:00
Asherah Connor 594d92f3fd build: include externals in deps. 2024-08-24 17:22:24 +03:00
Asherah Connor 2e4b50cce1 build: add externals to build plan. 2024-08-24 17:19:00 +03:00
Asherah Connor 99273cb385 project: add isinstance_list, fix up errors. 2024-08-24 17:07:03 +03:00
Asherah Connor cad501dda2 template: move to docs/. 2024-08-24 16:59:31 +03:00
Asherah Connor fdc3e5ec56 README: note. 2024-08-18 11:39:43 +03:00
Asherah Connor bf3738f777 project: add NIAR_WORKING_DIRECTORY support. 2024-08-18 11:27:27 +03:00
Asherah Connor 96df013632 rejig for Nix/pure. 2024-08-18 11:27:27 +03:00
Asherah Connor bca15c1ba5 CHANGELOG.md: prepare. 2024-08-07 12:43:17 +03:00
Asherah Connor b729590f81 release v0.1.2. 2024-08-07 12:43:00 +03:00
Asherah Connor ca6847c21c CHANGELOG: 0.1 -> 0.1.0. 2024-08-07 12:30:09 +03:00
Asherah Connor 15b4e93725 TODO: elaborate. 2024-08-07 11:52:11 +03:00
Asherah Connor 42b7bbede5 TODO: add. 2024-08-07 11:51:00 +03:00
Asherah Connor 11b388e18d README: add URL. 2024-08-07 11:47:26 +03:00
Asherah Connor 5d8553a241 build: fix path used with cached synthesis when programming. 2024-07-04 20:18:34 +03:00
Asherah Connor bb65ae312c pyproject.toml: use scm version. 2024-07-04 18:25:41 +03:00
Asherah Connor 318af1aeb7 style. 2024-07-04 18:19:38 +03:00
Asherah Connor 98ac6138b1 README: link CHANGELOG. 2024-07-04 18:19:09 +03:00
Asherah Connor 3f85a404af CHANGELOG: update. 2024-07-04 18:18:41 +03:00
Asherah Connor e2ffef5cc2 cxxrtl: always force for now. 2024-07-04 18:14:07 +03:00
Asherah Connor 954de5e69d build: fix comments. 2024-07-04 18:13:06 +03:00
Asherah Connor 445d0ed0c1 build: include timing info in output info. 2024-07-04 18:12:27 +03:00
Asherah Connor ef5d43b417 cxxrtl: note. 2024-07-03 19:19:30 +03:00
Asherah Connor a931d328be build: allow adding kwargs to prepare() call. 2024-07-03 19:19:27 +03:00
Asherah Connor 3d32cf809e build: synth depends on .ys as well. 2024-07-03 19:18:39 +03:00
Asherah Connor 289c0e96f9 template: use latest amaranth-yosys, now we can opt! 2024-07-03 16:34:17 +03:00
Asherah Connor 6ff5e58dbf CHANGELOG.md: update. 2024-07-03 13:27:51 +03:00
Asherah Connor 8175fb5d0a build: use IL from plan, not on disk. 
We haven't extracted it yet.
 2024-07-03 13:26:53 +03:00
Asherah Connor 12dc846334 template: add .pdm-python to .gitignore. 2024-07-02 14:10:29 +03:00
Asherah Connor 7572c3716a template: add lockfile. 2024-07-02 13:09:02 +03:00
Asherah Connor 94bddbd996 setup-action: rely on PDM, document. 2024-07-02 13:08:45 +03:00
Asherah Connor 404601a50a pyproject.toml: depend on upstream amaranth-boards, update lock and amaranth accordingly. 2024-07-02 13:00:10 +03:00
Asherah Connor 4db4fc2509 template: clean up template project. 2024-07-02 12:59:02 +03:00
Asherah Connor db7ca3b5d2 release v0.1.1. 2024-07-02 12:53:53 +03:00
Asherah Connor b57c9a5c25 pyproject.toml: depend on amaranth >= 0.5. 2024-07-02 12:48:02 +03:00
Asherah Connor 2381d6ef41
Merge pull request #1 from kivikakk/pdm 
use pdm fully.
 2024-07-02 12:42:59 +03:00
Asherah Connor 915b094cdb workflows: install OSS CAD Suite to test synth. 2024-07-02 12:39:16 +03:00
Asherah Connor 1fc3c5697d workflows: .venv/bin/. 2024-07-01 22:42:40 +03:00
Asherah Connor 222151cf55 use pdm fully. 2024-07-01 22:29:36 +03:00
Asherah Connor 596c60287d project: find root by looking for pyproject.toml. 2024-06-29 19:20:54 +03:00
Asherah Connor 6f62b50278 move to src layout. 2024-06-29 19:11:16 +03:00
Asherah Connor dc26ba8c44 cxxrtl: only write "opt" out when actually opt; write "noopt" otherwise. 2024-06-28 17:17:15 +03:00
Asherah Connor 359962b0fe cxxrtl: opt is between RTL and code. 
RTL used to mean "-O3 on the CXXRTL-generated .cc". Now it means running
an opt pass in Yosys. Code covers all code: C++ (and Zig if used).
 2024-06-28 16:44:13 +03:00