119 lines
5.7 KiB
Markdown
119 lines
5.7 KiB
Markdown
---
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title: "yosys4gal: a Yosys Synthesis flow for GAL chips"
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description: Bringing modern synthesis to 30-year old technology with Yosys and Rust.
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date: 2024-06-14
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---
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## A history lesson
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During the semiconductor revolution, a dilemma appeared: Designing new ICs
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required a lot of time and effort to create the mask, and iteration was
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expensive. At the time, IC designs were very simple, since the available
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tools/compute to do tasks like optimization or place-and-route were limited.
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And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs)
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were an early approach to these problems. The idea was simple: create a
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flexible logic architecture that could be modified later in the process to
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implement various digital designs. These worked by using matrices of wires in a
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Sum-of-Products architecture. Inputs would be fed with their normal and
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inverted forms to a bank of AND gates, which would select various inputs using
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a fuse tie on the die and create product terms. The outputs of the AND gates
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would then be fed into OR gates, which would create the sum term for the whole
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output.
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This design was popular, since it allowed for less-certain aspects of the chip
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to be moved to a later design process. Eventually, hardware people got jealous
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of the fast (for the time) compile-evaluate loops in software, and so PAL
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(Programmable Array Logic) was invented. These are similar to PLA logic, but
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the fuses are programmed using a simple programmer rather than a complex die
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process. This means that a developer with a pile of chips can program one, test
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it, make some adjustments, and then program the next. Later versions would
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solve the whole one-time-programmable aspect using UV-erasable EEPROM.
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Demands would increase further and flip-flops would be added, as well as
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feedback capability. This allows for very complex functions to be implemented,
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since you can chain "rows" of the output blocks. This culminated in the
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GAL22V10, which was an electronically-erasable, 22-pin programmable logic
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block, which had up to 10 outputs that could be registered and used for
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feedback.
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## Back To Today: GALs in the 21st Century
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These days, modern FPGA technology can be yours for a couple of bucks.
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Open-source toolchains allow fast, easy development, and the glut of Verilog
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resources online makes it easier than ever to enter the world of hardware
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design. But there are times when GALs might still be useful. For one, they
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start up instantly. Some FPGAs have a very fast one-time- programmable internal
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ROM, but this loses the "field-programmable" aspect which makes FPGAs
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desirable. In most cases the bitstream must be loaded from an external SPI
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flash. This can take up to a few seconds, which may not be acceptable if the
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logic is critical. Another important factor is the chip packaging. Most FPGAs
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are BGA packages, with some offering QFN or even a few QFP variants, but none
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are available in any DIP form factor, at least without a small board in
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between. The ATF22V10 (which is a clone/successor of the GAL22V10) is available
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in DIP, SSOP, and even PLCC if that's your jam. The package options make GALs
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perfect for breadboard applications. You could use it like an 8-in-1 74-series
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logic chip, changing the function depending on what you need. Additionally,
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GALs operate at 5 volts is useful when interfacing with older systems and
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removes the need for a level shifter.
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However, this isn't all great. Programming GALs is an exercise in frustration.
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Take a look at a basic combinatorial assembly file:
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```PALASM
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GAL16V8
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CombTest
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Clock I0 I1 I2 I3 I4 I5 NC NC GND
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/OE O0 O1 O2 O3 O4 I6 NC NC VCC
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O0 = I0 * I1
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O1 = I2 + I3 + I6
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O2 = I4 * /I5 + /I4 * I5
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O3 = I0 * I1 * I2 * I3 * I4 * I5
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/O4 = I0 + I1 + I2 + I3 + I4 + I5
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DESCRIPTION
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Simple test of combinatorial logic.
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```
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In the contrived example the behavior is pretty clear, but it's not exactly a
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stellar format for writing complex logic. Plus, there's no way to integrate or
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test this in a larger system (we'll get back to this). Compared to the Verilog
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flow, with simulation, testbenches, and synthesis, the raw assembly is stuck in
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the 80s and requires manual logic simplification.
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Verilog compilers for GALs *did exist*, but they ran on old-as-dirt systems,
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didn't have any significant optimization capabilities, and were almost always
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proprietary. What if we could make our own open-source Verilog flow for GAL
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chips? Then we could write test benches in Verilog, map complex designs onto
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the chip, and even integrate our designs with FPGAs later down the line.
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# The idea
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GAL assembly is still common
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# Is this useful?
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No, not really.
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Well, there's a very very niche use case. These parts are 5-volt tolerant, and come in DIP packages. If you needed some basic glue logic
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when working on an older 5 volt system, you might want to have a few of these + a programmer instead of a collection of 74-series logic.
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At the very least, these chips can emulate any 74-series chip, and can reduce a multi-chip design to a single chip.
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The DIP form factor makes it much easier to breadboard, and the chips have zero start up delay.
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In that narrow use case, `yosys4gal` is rather crucial. You no longer need WinCUPL or any old software, instead
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using Verilog + Yosys. Your designs are automatically optimized, which makes it easier to fit more complex logic. And since it's verilog,
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you can integrate it into a larger simulation or move it to an FPGA later if you desire.
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